Optoelectronic devices are well known and it is also known that for such devices it is desirable to minimise the occurrence of defects in the semiconductor layers that form part of the structure of the device. Common defects in LEDs, for example, include threading (edge or screw type) dislocations which lead to a reduced luminescent efficiency in the final product. The efficiency reduction can, at least in part, arise due to non-radiative recombination that can occur at dislocations and defects. These defects reduce the internal quantum efficiency (IQE) of the device.
One cause of such dislocations, as discussed in WO2006/014472, is lattice mismatches between dissimilar layers. Dislocations can arise simply due to different lattice parameters and/or due to thermal contraction at different rates following thermal growth techniques. One way to reduce the dislocation density is to rely on the growth of interlayers, as described in US2002/0069817. The technique described in US2002/0069817 relies in part on the growth of a thick layer of GaN.
A consequence of the mismatched lattice parameters and thermal expansion coefficients, particularly where the difference lies between the substrate and the overlying layers, is a high degree of curvature that is introduced into the wafer by the mismatch. This curvature affects the size of wafer that can be manufactured or leads to wafers with high defect levels.
If an overlying layer has a significantly larger thermal expansion coefficient than the substrate, the overlying layer would be in tension. This can lead to crack formation. For LED structures, where a GaN layer is preferably n-type doped, the doping adds additional tensile stress to the structure. As a consequence, stress management is critical, especially where Si substrates are used.
Several methods have been proposed to address the issue of tensile stress and associated curvation and/or cracking. Methods include the use of patterned substrates to guide the cracks in masked or etched parts of substrates, the use of compliant substrates, or the insertion of low-temperature AlN interlayers. US2010/0032650 discusses some of these techniques. It is, however, considered that to make, for example, GaN-based LEDs on Si substrates by a low-cost route, extra procedures such as ex-situ patterning before growth are not preferred, and a method is required that gives simultaneously crack-free layers, a low threading dislocation and a flat wafer.